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STM32L011E3 Fiches technique(PDF) 40 Page - STMicroelectronics |
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STM32L011E3 Fiches technique(HTML) 40 Page - STMicroelectronics |
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40 / 115 page ![]() DocID027973 Rev 4 40/115 STM32L011x3/4 Pin descriptions 42 - - - 26 28 28 - PB5 I/O FT - SPI1_MOSI, LPTIM1_IN1, I2C1_SMBA, TIM21_CH1 COMP2_INP - 18 - 27 29 29 A3 PB6 I/O FTf - USART2_TX, I2C1_SCL, LPTIM1_ETR, TIM2_CH3, LPUART1_TX COMP2_INP - 19 - 28 30 30 A4 PB7 I/O FTf - USART2_RX, I2C1_SDA, LPTIM1_IN2, TIM2_CH4, LPUART1_RX COMP2_INP, VREF_PVD_IN 1 201 131 31 A5 PB9-BOOT0 I B - - BOOT0 (Boot memory selection) ----- 32 - PB8 I/O FTf - USART2_TX, EVENTOUT, I2C1_SCL, SPI1_NSS - ---- 32 -- VSS S - (5) -- ---- 1 1 - VDD S - (6) -- 1. VSS pins are connected to the exposed pad (see Figure 36: UFQFPN32, 5 x 5 mm, 32-pin package outline). 2. Device reset input/internal reset output (active low). 3. Analog power supply. 4. On TSSOP14 package, VDDA is internally connected to VDD. 5. Digital and analog ground. 6. Digital power supply. Table 13. Pin definitions (continued) Pin number Pin name (function after reset) Notes Pin functions Alternate functions Additional functions |
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