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GL811USB Fiches technique(PDF) 7 Page - List of Unclassifed Manufacturers

No de pièce GL811USB
Description  USB 2.0 to ATA / ATAPI Bridge Controller
PDF  36 Pages
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Fabricant  ETC [List of Unclassifed Manufacturers]
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GL811USB Fiches technique(HTML) 7 Page - List of Unclassifed Manufacturers

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GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller
©2000-2002 Genesys Logic Inc.—All rights reserved.
Page 6
3.2.8 FIFOs
Control FIFO is used as Control Read / Write FIFO. TXFIFO0 / TXFIFO1 are two
sets of 512-byte ping-pong FIFO for Bulk Read endpoint. It buffers data from IDE
engine, and re-direct to USB SIE logic. RXFIFO0 / RXFIFO1 are two sets of
512-byte ping-pong FIFO for Bulk Write endpoint. It buffers data from USB SIE
logic, and re-direct to IDE engine.
3.2.9 Control Registers
Control Register configures GL811USB to proper operation. For example, CPU
can set register to generate wakeup event, enter suspend, transmits proper USB
packet to host.



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