FEDL610Q421-03

ML610Q421/ML610Q422

• LCD driver

− Dot matrix can be supported.

ML610Q421: 400 dots max. (50 seg

× 8 com), 1/1 to 1/8 duty

ML610Q422: 800 dots max. (50 seg

× 16 com) , 1/1 to 1/16 duty

− 1/3 or 1/4 bias (built-in bias generation circuit)

− Frame frequency selecable (approx. 64 Hz, 73 Hz, 85 Hz, and 102 Hz)

− Bias voltage multiplying clock selectable (8 types)

− Contrast adjustment (1/3 bias: 32 steps, 1/4 bias: 20 steps)

− LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable

− Programmable display allocation function (available only when 1/1~1/8 duty is selected)

• Reset

− Reset through the RESET_N pin

− Power-on reset generation when powered on

− Reset when oscillation stop of the low-speed clock is detected

− Reset by the watchdog timer (WDT) overflow

• Power supply voltage detect function

− Judgment voltages:

One of 16 levels

− Judgment accuracy:

±2% (Typ.)

• Clock

− Low-speed clock: (This LSI can not guarantee the operation withoug low-speed clock)

Crystal oscillation (32.768 kHz)

− High-speed clock:

Built-in RC oscillation (500 kHz)

Built-in PLL oscillation (8.192 MHz

±2.5%), crystal/ceramic oscillation (4.096 MHz), external clock

− Selection of high-speed clock mode by software:

Built-in RC oscillation, built-in PLL oscillation, crystal/ceramic oscillation, external clock

• Power management

− HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states).

− STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are

stopped.)

− Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation

clock)

− Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused peripherals.

• Guaranteed operating range

− Operating temperature: −20°C to 70°C (P version: −40°C to +85°C)

− Operating voltage: V

3/37