TMS320C6711 datasheet(21/129 Pages) TI

21 / 129 page

TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088L − FEBRUARY 1999 − REVISED MAY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

DEVICE CONFIGURATIONS (CONTINUED)

DEVCFG register description [C6711C/C6711D only]

The device configuration register (DEVCFG) allows the user control of the EMIF input clock source for the

C6711C/C6711D device only. For more detailed information on the DEVCFG register control bits, see Table 16

and Table 17.

Table 16. Device Configuration Register (DEVCFG) [Address location: 0x019C0200 − 0x019C02FF]

Reserved†

RW-0

Reserved†

EKSRC

Reserved†

RW-0

R/W-0

Legend: R/W = Read/Write; -n = value after reset

† Do not write non-zero values to these bit locations.

Table 17. Device Configuration (DEVCFG) Register Selection Bit Descriptions

BIT #

NAME

DESCRIPTION

31:5

Reserved

Reserved. Do not write non-zero values to these bit locations.

EKSRC

EMIF input clock source bit.

Determines which clock signal is used as the EMIF input clock.

0 = SYSCLK3 (from the clock generator) is the EMIF input clock source (default)

1 = ECLKIN external pin is the EMIF input clock source

3:0

Reserved

Reserved. Do not write non-zero values to these bit locations.

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