LP5526TLSLASHNOPB datasheet(7/41 Pages) TI1

7 / 41 page

LP5526

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SNVS431D – FEBRUARY 2006 – REVISED MARCH 2013

DETAILED DESCRIPTION

Modes of Operation

RESET: In the RESET mode all the internal registers are reset to the default values. Reset is entered always if

input NRST is LOW or internal Power On Reset is active. Power On Reset (POR) will activate during the

chip startup or when the supply voltages VDD1 and VDD2 fall below 1.5V. Once VDD1 and VDD2 rises above

1.5V, POR will inactivate and the chip will continue to the STANDBY mode. NSTBY control bit is low after

POR by default.

STANDBY: The STANDBY mode is entered if the register bit NSTBY is LOW and Reset is not active. This is the

low power consumption mode, when all circuit functions are disabled. Registers can be written in this

mode and the control bits are effective immediately after start up.

STARTUP: When NSTBY bit is written high, the INTERNAL STARTUP SEQUENCE powers up all the needed

internal blocks (VREF, Bias, Oscillator etc.). To ensure the correct oscillator initialization, a 10ms delay is

generated by the internal state-machine. If the chip temperature rises too high, the Thermal Shutdown

(TSD) disables the chip operation and STARTUP mode is entered until no thermal shutdown event is

present.

BOOST STARTUP: Soft start for boost output is generated in the BOOST STARTUP mode. The boost output is

raised in low current PWM mode during the 20ms delay generated by the state-machine. All LED outputs

are off during the 20ms delay to ensure smooth startup. The Boost startup is entered from Internal Startup

Sequence if EN_BOOST is HIGH or from Normal mode when EN_BOOST is written HIGH.

NORMAL: During NORMAL mode the user controls the chip using the Control Registers. The registers can be

written in any sequence and any number of bits can be altered in a register in one write.

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LP5526TL/NOPB Fiches technique(PDF) 7 Page - Texas Instruments