CS4244 datasheet(21/63 Pages) CIRRUS

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DS900F2

CS4244

SWITCHING SPECIFICATIONS - CONTROL PORT

Test conditions (unless otherwise specified): Inputs: Logic 0 = GND = 0 V, Logic 1 = VL; SDA load capacitance equal to maxi-

mum value of Cb specified below (Note 30).

Notes:

30. All specifications are valid for the signals at the pins of the CS4244 with the specified load capacitance.

31. 2 ms + (3000/MCLK). See Section 4.2.1.

32. Data must be held for sufficient time to bridge the transition time, tf, of SCL.

Parameters

Symbol

Min

Max

Unit

SCL Clock Frequency

fscl

550

kHz

RESET Rising Edge to Start

tirs

(Note 31)

-ns

Bus Free Time Between Transmissions

tbuf

1.3

µs

Start Condition Hold Time (prior to first clock pulse)

thdst

0.6

µs

Clock Low time

tlow

1.3

µs

Clock High Time

thigh

0.6

µs

Setup Time for Repeated Start Condition

tsust

0.6

µs

SDA Input Hold Time from SCL Falling

(Note 32)

thddi

00.9

µs

SDA Output Hold Time from SCL Falling

thddo

0.2

0.9

µs

SDA Setup time to SCL Rising

tsud

100

Rise Time of SCL and SDA

-300

Fall Time SCL and SDA

-300

Setup Time for Stop Condition

tsusp

0.6

µs

SDA Bus Load Capacitance

-400

SDA Pull-Up Resistance

500



t buf

t hdst

low

t r

t f

hdd

t high

t sud

tsust

t susp

Stop

Start

Stop

Repeated

SDA

SCL

t irs

RST

Figure 8. I²C Control Port Timing

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