DP83916 datasheet(2/96 Pages) NSC

2 / 96 page

Table of Contents

10 FUNCTIONAL DESCRIPTION

11 IEEE 8023 ENDEC Unit

111 ENDEC Operation

112 Selecting an External ENDEC

12 MAC Unit

121 MAC Receive Section

122 MAC Transmit Section

13 Byte Ordering

14 FIFO and Control Logic

141 Receive FIFO

142 Transmit FIFO

15 Status and Configuration Registers

16 Bus Interface

17 Loopback and Diagnostics

171 Loopback Procedure

18 Network Management Functions

20 TRANSMITRECEIVE IEEE 8023

FRAME FORMAT

21 Preamble and Start Of Frame Delimiter (SFD)

22 Destination Address

23 Source Address

24 LengthType Field

25 Data Field

26 FCS Field

27 MAC (Media Access Control) Conformance

30 BUFFER MANAGEMENT

31 Buffer Management Overview

32 Descriptor Areas

321 Naming Convention for Descriptors

322 Abbreviations

323 Buffer Management Base Address

33 Descriptor Data Alignment

34 Receive Buffer Management

341 Receive Resource Area (RRA)

342 Receive Buffer Area (RBA)

343 Receive Descriptor Area (RDA)

344 Receive Buffer Management Initialization

345 Beginning of Reception

346 End of Packet Processing

347 Overflow Conditions

35 Transmit Buffer Management

351 Transmit Descriptor Area (TDA)

352 Transmit Buffer Area (TBA)

353 Preparing to Transmit

354 Dynamically Adding TDA Descriptors

40 SONIC-16 REGISTERS

41 The CAM Unit

411 The Load CAM Command

42 StatusControl Registers

43 Register Description

431 Command Register

432 Data Configuration Register

433 Receive Control Register

434 Transmit Control Register

435 Interrupt Mask Register

436 Interrupt Status Register

437 Data Configuration Register 2

438 Transmit Registers

439 Receive Registers

4310 CAM Registers

4311 Tally Counters

4312 General Purpose Timer

4313 Silicon Revision Register

50 BUS INTERFACE

51 Pin Configurations

52 Pin Description

53 System Configuration

54 Bus Operations

541 Acquiring the Bus

542 Block Transfers

543 Bus Status

544 Bus Mode Compatibility

545 Master Mode Bus Cycles

546 Bus Exceptions (Bus Retry)

547 Slave Mode Bus Cycle

548 On-Chip Memory Arbiter

549 Chip Reset

60 NETWORK INTERFACING

61 Manchester Encoder and Differential Driver

611 Manchester Decoder

612 Collision Translator

613 Oscillator Inputs

70 AC AND DC SPECIFICATIONS

80 AC TIMING TEST CONDITIONS

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