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DP8390DV Fiches technique(PDF) 40 Page - National Semiconductor (TI) |
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DP8390DV Fiches technique(HTML) 40 Page - National Semiconductor (TI) |
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40 / 56 page ![]() 150 Switching Characteristics (Continued) Register Read (Non Latched ADS0 e 1) TLF8582 – 77 Symbol Parameter Min Max Units rsrs Register Select to Read Setup 10 ns (Notes 1 3) rsrh Register Select Hold from Read 0 ns ackdv ACK Low to Valid Data 55 ns rdz Read Strobe to Data TRI-STATE 15 70 ns (Note 2) rackl Read Strobe to ACK Low (Note 3) n bcyc a 30 ns rackh Read Strobe to ACK High 30 ns Note 1 rsrs includes flow-through time of latch Note 2 These limits include the RC delay inherent in our test method These signals typically turn off within 15 ns enabling other devices to drive these lines with no contention Note 3 CS may be asserted before or after RA0–3 and SRD since address decode begins when ACK is asserted If CS is asserted after RA0-3 and SRD rack1 is referenced from falling edge of CS 40 |
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