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AD6635BB/PCB Fiches technique(PDF) 10 Page - Analog Devices

No de pièce AD6635BB/PCB
Description  4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP)
PDF  60 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD6635BB/PCB Fiches technique(HTML) 10 Page - Analog Devices

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REV. 0
–10–
AD6635
MICROPROCESSOR PORT TIMING CHARACTERISTICS1, 2
Test
AD6635BB
Parameter (Conditions)
Temp
Level
Min
Typ
Max
Unit
MICROPROCESSOR PORT, MODE MNM (MODE = 0)
MODE INM WRITE TIMING
tSC
Control
3 to
≠CLKn Setup Time
Full
IV
2.0
ns
tHC
Control
3 to
≠CLKn Hold Time
Full
IV
2.5
ns
tHWR
WR(RW) to RDY(DTACK) Hold Time
Full
IV
7.0
ns
tSAM
Address/Data to
WR(RW) Setup Time
Full
IV
3.0
ns
tHAM
Address/Data to RDY(
DTACK) Hold Time
Full
IV
5.0
ns
tDRDY
WR(RW) to RDY(DTACK) Delay
Full
IV
8.0
ns
tACC
WR(RW) to RDY(DTACK) High Delay
Full
IV
4
tCLK
5
tCLK
9
tCLK
ns
MODE INM READ TIMING
tSC
Control
3 to
≠CLKn Setup Time
Full
IV
5.0
ns
tHC
Control
3 to
≠CLKn Hold Time
Full
IV
2.0
ns
tSAM
Address to
RD(DS) Setup Time
Full
IV
0.0
ns
tHAM
Address to Data Hold Time
Full
IV
5.0
ns
tDRDY
RD(DS) to RDY(DTACK) Delay
Full
IV
8.0
ns
tACC
RD(DS) to RDY(DTACK) High Delay
Full
IV
8
tCLK
10
tCLK 13
tCLK
ns
MICROPROCESSOR PORT, MODE MNM (MODE = 1)
MODE MNM WRITE TIMING
tSC
Control
3 to
≠CLKn Setup Time
Full
IV
2.0
ns
tHC
Control
3 to
≠CLKn Hold Time
Full
IV
2.5
ns
tHDS
DS(RD) to DTACK(RDY) Hold Time
Full
IV
8.0
ns
tHRW
RW(
WR) to DTACK(RDY) Hold Time
Full
IV
7.0
ns
tSAM
Address/Data to RW(
WR) Setup Time
Full
IV
3.0
ns
tHAM
Address/Data to RW(
WR) Hold Time
Full
IV
5.0
ns
tDDTACK DS(RD) to DTACK(RDY) Delay
Full
IV
8.0
ns
tACC
RW(
WR) to DTACK(RDY) Low Delay
Full
IV
4
tCLK
5
tCLK
9
tCLK
ns
MODE MNM READ TIMING
tSC
Control
3 to
≠CLKn Setup Time
Full
IV
5.0
ns
tHC
Control
3 to
≠CLKn Hold Time
Full
IV
2.0
ns
tHDS
DS(RD) to DTACK(RDY) Hold Time
Full
IV
8.0
ns
tSAM
Address to
DS(RD) Setup Time
Full
IV
0.0
ns
tHAM
Address to Data Hold Time
Full
IV
5.0
ns
tDDTACK DS(RD) to DTACK(RDY) Delay
Full
IV
8.0
ns
tACC
DS(RD) to DTACK(RDY) Low Delay
Full
IV
8
tCLK
10
tCLK 13
tCLK
ns
NOTES
1All Timing Specifications valid over VDD range of 2.25 V to 2.75 V, and VDDIO range of 3.0 V to 3.6 V.
2C
LOAD = 40 pF on all outputs unless otherwise specified.
3Specification pertains to control signals: R/W, (
WR), DS, (RD), CS0, CS1.
Specifications subject to change without notice.



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