AD5641 datasheet(4/20 Pages) AD

No de pièce	AD5641

Description	2.7 V to 5.5 V, <100 uA, 14-Bit nanoDAC D/A in SC70 Package

PDF	20 Pages

Scroll/Zoom	100%

Fabricant	AD [Analog Devices]

Site Internet	http://www.analog.com

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AD5641

Preliminary Technical Data

Rev. PrC | Page 4 of 20

TIMING CHARACTERISTICS

VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. See Figure 2.

Table 3.

Parameter

Limit1

Unit

Test Conditions/Comments

t12

ns min

SCLK cycle time

ns min

SCLK high time

ns min

SCLK low time

ns min

SYNC to SCLK falling edge setup time

ns min

Data setup time

4.5

ns min

Data hold time

ns min

SCLK falling edge to SYNC rising edge

ns min

Minimum SYNC high time

ns min

SYNC rising edge to next SCLK fall ignore

1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

2 Maximum SCLK frequency is 30 MHz.

D14

D15

DIN

SYNC

SCLK

D15

D14

Figure 2. Timing Diagram

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