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74LVC2G38DP Fiches technique(PDF) 10 Page - NXP Semiconductors |
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74LVC2G38DP Fiches technique(HTML) 10 Page - NXP Semiconductors |
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10 / 15 page ![]() 2004 Oct 18 10 Philips Semiconductors Product specification Dual 2-input NAND gate (open drain) 74LVC2G38 handbook, full pagewidth VEXT VCC VI VO MNA616 D.U.T. CL RT RL RL PULSE GENERATOR Fig.7 Load circuitry for switching times. Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VCC VI CL RL VEXT tPLH/tPHL tPZH/tPHZ tPZL/tPLZ 1.65 V to 1.95 V VCC 30 pF 1 k Ω open GND 2 × VCC 2.3 V to 2.7 V VCC 30 pF 500 Ω open GND 2 × VCC 2.7 V 2.7 V 50 pF 500 Ω open GND 6 V 3.0 V to 3.6 V 2.7 V 50 pF 500 Ω open GND 6 V 4.5 V to 5.5 V VCC 50 pF 500 Ω open GND 2 × VCC |
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