ADS5273IPFP datasheet(9/33 Pages) TI1

9 / 33 page

NOTE: The shown power−up time is based on 1

µF bypass capacitors on the reference pins.

See the Theory of Operation section for details.

Device Fully

Powers Down

Device Fully

Powers Up

500

µs

SERIAL INTERFACE TIMING

Start Sequence

(MSB)

ADCLK

SCLK

SDATA

Outputs change on

next rising clock edge

after CS goes high.

Data latched on

each rising edge of SCLK.

NOTE: Data is shifted in MSB first.

ADS5273

www.ti.com .............................................................................................................................................. SBAS305D – JANUARY 2004 – REVISED JANUARY 2009

POWER-DOWN TIMING

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNIT

Serial CLK Period

Serial CLK High Time

Serial CLK Low Time

Data Setup Time

Data Hold Time

CS Fall to SCLK Rise

SCLK Rise to CS Rise

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