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MPC875 Fiches technique(PDF) 60 Page - Freescale Semiconductor, Inc

No de pièce MPC875
Description  Hardware Specifications
PDF  84 Pages
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Fabricant  FREESCALE [Freescale Semiconductor, Inc]
Site Internet  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC875 Fiches technique(HTML) 60 Page - Freescale Semiconductor, Inc

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MPC875/MPC870 Hardware Specifications, Rev. 3.0
60
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
CPM Electrical Characteristics
Figure 55. Ethernet Collision Timing Diagram
Figure 56. Ethernet Receive Timing Diagram
133
TENA active delay (from TCLK3 rising edge)
10
50
ns
134
TENA inactive delay (from TCLK3 rising edge)
10
50
ns
138
CLKO1 low to SDACK asserted 2
—20
ns
139
CLKO1 low to SDACK negated 2
—20
ns
1 The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater than or equal to 2/1.
2 SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.
Table 24. Ethernet Timing (continued)
Num
Characteristic
All
Frequencies
Unit
Min
Max
CLSN(CTS1)
120
(Input)
RCLK3
121
RxD3
(Input)
121
RENA(CD3)
(Input)
125
124
123
127
126
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