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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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MAC7100 Fiches technique(PDF) 30 Page - Motorola, Inc |
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MAC7100 Fiches technique(HTML) 30 Page - Motorola, Inc |
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30 / 48 page  30 MAC7100 Microcontroller Family Hardware Specifications MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Electrical Characteristics 3.11 Serial Peripheral Interface Electrical Specifications 3.11.1 Master Mode Figure 11 and Figure 12 illustrate master mode timing. Timing values are shown in Table 33. 3.11.2 Slave Mode Figure 13 and Figure 14 illustrate the slave mode timing. Timing values are shown in Table 34. Table 33. SPI Master Mode Timing Characteristics 1 1 The numbers 7, 8 in the column labeled “Num” are missing. This has been done on purpose to be consistent between the Master and the Slave timing shown in Table 34. Conditions are shown in Table 6 unless otherwise noted, CLOAD = 200pF on all outputs Num C Rating Symbol Min Typ Max Unit W1a P Operating Frequency fop DC — 1 /4fbus W1b P SCK Period tsck = 1/fop tsck 4 — 2048 tbus W2 D Enable Lead Time tlead 1 /2— — tsck W3 D Enable Lag Time tlag 1 /2— — tsck W4 D Clock (SCK) High or Low Time twsck tbus − 30 — 1024 tbus ns W5 D Data Setup Time (Inputs) tsu 25 — — ns W6 D Data Hold Time (Inputs) thi 0— — ns W9 D Data Valid (after Enable Edge) tv —— 25 ns W10 D Data Hold Time (Outputs) tho 0— — ns W11 D Rise Time Inputs and Outputs tr —— 25 ns W12 D Fall Time Inputs and Outputs tf —— 25 ns Table 34. SPI Slave Mode Timing Characteristics Conditions are shown in Table 6 unless otherwise noted, CLOAD = 200pF on all outputs Num C Rating Symbol Min Typ Max Unit X1a P Operating Frequency fop DC — 1 /4fbus X1b P SCK Period tsck = 1/fop tsck 4 — 2048 tbus X2 D Enable Lead Time tlead 1— — tcyc X3 D Enable Lag Time tlag 1— — tcyc X4 D Clock (SCK) High or Low Time twsck tcyc − 30 — — ns X5 D Data Setup Time (Inputs) tsu 25 — — ns X6 D Data Hold Time (Inputs) thi 25 — — ns X7 D Slave Access Time ta —— 1 tcyc X8 D Slave SIN Disable Time tdis —— 1 tcyc X9 D Data Valid (after SCK Edge) tv —— 25 ns X10 D Data Hold Time (Outputs) tho 0— — ns X11 D Rise Time Inputs and Outputs tr —— 25 ns X12 D Fall Time Inputs and Outputs tf —— 25 ns Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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