CLC5523IM datasheet(7/12 Pages) NSC

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Minimizing Parasitic Effects on

Small Signal Bandwidth

The best way to minimize parasitic effects is to use the

small outline package and surface mount components.

For

designs

utilizing

through-hole

components,

specifically axial resistors, resistor self-capacitance

should be considered. Example: the average magnitude

of parasitic capacitance of RN55D 1% metal film

resistors is about 0.15pF with variations of as much as

0.1pF between lots.

Given the CLC5523’s extended

bandwidth, these small parasitic reactance variations can

cause measurable frequency response variations in the

highest octave. We therefore recommend the use

of surface mount resistors to minimize these parasitic

reactance effects. If an axial component is preferred, we

recommend PRP8351 resistors which are available from

Precision Resistive Products, Inc., Highway 61 South,

Mediapolis, Iowa.

Small Signal Response at Low Avmax

When the maximum gain, as set by Rg and Rf, is greater

than or equal to Avmax = 10, little or no peaking should be

observed in the amplifier response. When the gain range

is set to less than Avmax = 10, some peaking may

be observed at higher frequencies. At gain ranges of

² Avmax ² 10 peaking can be minimized by increasing

Rf.

At gain ranges of Avmax < 2 peaking reaches

approximately 6dB in the upper octave.

If peaking is observed with the recommended Rf resistor,

and a small increase in the Rf resistor does not solve the

problem, then investigate the possible causes and

remedies listed below.

Capacitance across Rf

Do not place a capacitor across Rf

Keep traces connecting Rf separated and as

short as possible

Capacitive Loads

Place a small resistor (20-50

W) between the

output and CL

Long traces and/or lead lengths between Rf

and the CLC5523

Keep these traces as short as possible

Long traces between CLC5523 and 0.1

bypass capacitors

Keep these traces less than 0.2 inches (5mm)

For the devices in the PDIP package, an

additional 1000pF monolithic capacitor should be

placed less than 0.1” (3mm) from the pin

Extra capacitance between the Rg pin and

ground (CG)

See the

Printed Circuit Board Layout sub-section

below for suggestions on reducing CG

Increase Rf if peaking is still observed after

reducing CG

Non-inverting input pin connected directly to

ground

Place a 50 to 200

W resistor between the non-

inverting pin and ground

Adjusting Offsets and DC Level Shifting

Offsets can be broken into two parts: an input-referred term

and an output-referred term. These errors can be trimmed

using the circuit in Figure 4. First set VG to 0V and adjust

the trim pot R4 to null the offset voltage at the output. This

will eliminate the output stage offsets. Next set VG to 2V

and adjust the trim pot R1 to null the offset voltage at the

output. This will eliminate the input stage offsets.

Figure 4: Offset Adjust Circuit

CLC5523

10k

0.1

10k

-5V

+5V

Vin

10k

0.1

10k

-5V

+5V

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