CLC532ALC datasheet(8/12 Pages) NSC

8 / 12 page

mode.

The CLC532 output signal can be slew limited by using

its compensation capacitors.

This approach also

has the

advantage of limiting

the excess noise passed through the

CLC532 and on to the ADC. Figure 7 shows the recommended

COMP values as a function of ADC Sample rate. Since the optimal

values will change from one ADC to the next, this graph should

be used as a starting point for C

COMP

selection. Both C

COMP

capacitors should be the same value to maintain output symmetry.

Flash ADCs are similar to subranging ADCs in that the sampling

period is very brief. The primary difference is that the acquisition

time of a flash converter is much shorter than that of a subranging

ADC. With a flash ADC, the transition of the CLC532 output

should be after the sampling instant ("Aperture Delay" after the

CONVERT command). It is only during this period that a flash

converter is susceptible to interference from a rapidly changing

analog input signal.

Gain Selection for an ADC

In many applications, such as RADAR, the dynamic range

requirements may exceed the accuracy requirements. Since

wide dynamic range ADCs are also typically highly accurate

ADCs, this often leads the designer into selecting an ADC which

is a technical overkill and a budget buster. By using the CLC532

as a selectable-gain stage, a less expensive ADC can be used.

As an example, if an application calls for 80dB of dynamic Range

and 0.05% accuracy, rather than using a 14-bit converter, a 12-

bit converter combined with the circuit in figure 8 will meet the

same objective. The CLC532 is used to select between the

analog input signal and a version of the input signal attenuated

by 12dB.

This circuit affords 14-bit dynamic range, 12-bit

accuracy and 12-bit ease of implementation.

CLC532

Gain

SELECT

0.1 F

48.7

DGND

-5.2V

0.1

µF

+5V

REF

+6.8

10pF

Ω

OUT

Ω

Load

Ω

Source

Ω

200

Ω

66.6

Ω

Source

Input

INB

Figure 8: Selectable Gain Stage Improves

ADC Dynamic Range

Full Wave Rectifier Circuit

The use of a diode rectifier provides significant distortion for

signals that are small compared to the forward bias voltage.

Accordingly, when low distortion performance is needed, standard

diode based circuits do not work well. The CLC532 can be

configured to provide a very low distortion full wave rectifier. The

circuit in figure 9 is used to select between an analog input signal

and an inverted version of the input signal. The resulting output

exhibits very little distortion for small scale signals up to several

hundred kilohertz.

10114

Ω

-2V

OUT

CLC532

0.1

µF

-1

+20

RECTIFIER

INPUT

Zero Crossing

Treshold

Detector

Figure 9: Low Distortion Full Wave Rectifier

Use of the CLC532 as a Mixer.

A double balanced mixer, such as is shown in figure 10, operates

by multiplying the RF input by the LO input. This is done by using

the LO to select one of two paths through a diode bridge

depending upon the LO sign. The result is an output where IF=RF

when LO>0 and IF=-RF if LO<0.

This same result can be

obtained with the circuit shown in figure 11. The CLC532 based

circuit uses a digital LO making system design easier in those

cases where the LO is digitally derived. One advantage of the

CLC532 based approach is excellent isolation between all three

ports. Also see the

RF design awards article by Thomas Hack

in the January 1993 issue of

RF Design.

INPUT

OUTPUT

Figure 10: Typical Double-Balanced Mixer

IF OUTPUT

200

Ω

MINI-CIRCUITS

T4-1T

CLC532

RF INPUT

DIGITAL

LO INPUT

Figure 11: High-Isolation Mixer Implementation

Evaluation Board

An evaluation board (part number CLC730028) for the CLC532

is available.

This board can be used for fast, trouble-free,

evaluation and characterization of the CLC532. Additionally,

this board serves as a template for layout and fabrication

information. The CLC532 evaluation board data sheet is available.

http://www.national.com

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