CGS410 datasheet(2/18 Pages) NSC

2 / 18 page

Table of Contents

10 FUNCTIONAL DESCRlPTION

20 PIN DEFlNlTIONS

30 CIRCUIT OPERATION

31 Internal VCO Operation

311 VCO Tuning Characteristics

32 Crystal Oscillator Operation

33 Phase Comparator Operation

34 Programmable Divider Operation

35 Control Register Operation

351 System Loading Sequence

352 Structure of the Internal Serial Control Register

353 Power-up conditions

36 Loop Filter Characteristics

361 Loop FiIter Calculations

37 Clock Deglitching Considerations

38 Configurable Differential Output Buffers

39 Termination Considerations

310 System Interface Considerations

311 Applications

312 InputOutput Structures

40 DEVICE SPEClFICATIONS

41 Absolute Maximum Ratings

42 Recommended Operating Conditions

43 DC Electrical Characteristics

44 AC EIectrical Characteristics

45 Timing Issues

LIST OF FIGURES

Connection Diagram

CGS410 Block Diagram

Figure 3-1

Linear Operating Range

Figure 3-2

Phase Comparator ChargePump

Figure 3-3

Control Register Read Operations

Figure 3-4

Control Register Write Operations

Figure 3-5

Control Register Architecture

Figure 3-6

Bode Plot of Loop Filter Response

Figure 3-7

External Low Pass Filter

Figure 3-8

Termination

Figure 3-9

Pull-upPull-down DC Termination

Figure 3-10 Typical Termination (Bit 1 e 0)

Figure 3-11 PCLKPCLKB Load vs Frequency

Figure 3-12 Serial Interface Example

Figure 3-13 Minimum Cost k80 MHz CGS410

Implementation

Figure 3-14 Common Video Application

Figure 3-15 Primary Loop GENLOCK Configuration

Figure 3-16 Crystal Configuration

Figure 3-17 CGS410 Using an External Loop Filter and

VCO

Figure 3-18 External XTLIN Drive Options

Figure 4-1

System Read Timing Specification

Figure 4-2

System Write Timing Specification

Figure 4-3

LCLK

EN Timing Specification

Figure 4-4

CMOS PCLK Output Skew Timing Specification

Figure 4-5

DIFF PCLK Output Skew Timing Specification

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