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CD4528BCN Fiches technique(PDF) 5 Page - National Semiconductor (TI) |
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CD4528BCN Fiches technique(HTML) 5 Page - National Semiconductor (TI) |
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5 / 8 page ![]() Logic Diagrams ( of Device Shown) Note Externally ground pins 1 and 15 to pin 8 TLF5998 – 3 TLF5998 – 4 TLF5998 – 10 Duty Cycle e 50% FIGURE 1 Power Dissipation Test Circuit and Waveforms TLF5998 – 5 Input Connections Characteristics CD AB tPLH tPHL tr tf VDD PG1 VDD PWout PWin tPLH tPHL tr tf VDD VSS PG2 PWout PWin tPLH(R) tPHL(R) PWin PG3 PG1 PG2 Includes capacitance of probes wir- ing and fixture parasitic Note AC test waveforms for PG1 PG2 and PG3 on next page TLF5998 – 6 FIGURE 2 AC Test Circuit 5 |
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