ADC12D040EVAL datasheet(9/22 Pages) NSC

No de pièce	ADC12D040EVAL

Description	Dual 12-Bit, 40 MSPS, 600 mW A/D Converter with Internal/External Reference and Sample-and-Hold

PDF	22 Pages

Scroll/Zoom	100%

Fabricant	NSC [National Semiconductor (TI)]

Site Internet	http://www.national.com

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9 / 22 page

AC Electrical Characteristics (Continued)

Note 11: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative

full-scale.

Note 12: Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge.

Note 13: Optimum performance will be obtained by keeping the reference input in the 1.8V to 2.2V range. The LM4051CIM3-ADJ (SOT-23 package) is

recommended for this application.

Note 14: IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage,

VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0 xf0 +C1 xf1 +....C11 xf11) where VDR is the output driver power supply

voltage, Cn is total capacitance on the output pin, and fn is the average frequency at which that pin is toggling.

Note 15: Excludes IDR. See note 14.

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