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PI6LC48P21 Fiches technique(PDF) 1 Page - Pericom Semiconductor Corporation |
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PI6LC48P21 Fiches technique(HTML) 1 Page - Pericom Semiconductor Corporation |
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1 / 7 page ![]() 1 www.pericom.com PI6LC48P21 Rev. A 06/19/13 PI6LC48P21 Pin Configuration Block Diagram Description The PI6LC48P21 is a single output LVPECL synthesizer opti- mized to generate Ethernet reference clock frequencies and is a member of Pericom’s HiFlex family of high performance clock solutions. Using a 25MHz or 26.6MHz crystal, it can generate 125MHz or 133MHz output frequencies. The PI6LC48P21 uses Pericom’s proprietary low phase noise PLL technology to achieve ultra low phase jitter, so it is ideal for Ethernet interface in all kind of systems. Features Î Î Single differential LVPECL output Î Î Supports the following output frequencies: 125MHz or 133MHz Î Î RMS phase jitter @ 125MHz, using a 25MHz crystal (12kHz – 20MHz): 0.3ps (typical) Î Î Full 3.3V or 2.5V supply modes Î Î Commercial and industrial ambient operating temperature Î Î Available in lead-free package: 8-TSSOP Applications Î Î Networking systems PFD VCO /25 OSC XTAL_OUT XTAL_IN /5 CLK CLK# Single Output LVPECL Clock Generator 1 2 3 4 VDD CLK# NC 8 7 6 5 CLK XTAL_IN XTAL_OUT VDDA GND 13-0096 |
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