IDT71V67802 datasheet(18/22 Pages) IDT

No de pièce	IDT71V67802

Description	256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Single Cycle Deselect

PDF	22 Pages

Scroll/Zoom	100%

Fabricant	IDT [Integrated Device Technology]

Site Internet	http://www.idt.com

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18 / 22 page

6.42

IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous

Commercial and Industrial Temperature Ranges

SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect

CLK

ADSP

GW,BWE,BWx

CE, CS1

CS0

ADDRESS

ADSC

DATAOUT

(Av)

(Aw)

(Ax)

(Ay)

5311 drw 14

Non-Burst Read Cycle Timing Waveform

NOTES:

1. ZZ input is LOW,

ADV is HIGH and LBO is Don't Care for this cycle.

2. (Ax) represents the data for address Ax, etc.

3. For read cycles,

ADSP and ADSC function identically and are therefore interchangable.

NOTES:

1. ZZ input is LOW,

ADV and OE are HIGH, and LBO is Don't Care for this cycle.

2. (Ax) represents the data for address Ax, etc.

3. Although only

GW writes are shown, the functionality of BWE and BWx together is the same as GW.

4. For write cycles,

ADSP and ADSC have different limitations.

Non-Burst Write Cycle Timing Waveform

CLK

ADSP

CE, CS1

CS0

ADDRESS

ADSC

DATAIN

(Av)

(Aw)

(Ax)

(Az)

(Ay)

5311 drw 15

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