Data Sheet TLE 6230 GP

V2.1

Page

26. Aug. 2002

8

Power Transistor Protection Functions

8)

Each of the eight output stages has its own zener clamp, which causes a voltage limitation at

the power transistor when solenoid loads are switched off. The outputs are provided with a

current limitation set to a minimum of 1 A. The continuous current for each channel is 500 mA

(all channels ON).

Each output is protected by embedded protection functions. In the event of an overload or

short to supply, the current is internally limited and the corresponding bit combination is set

(early warning). If this operation leads to an overtemperature condition, a second protection

level (about 170 °C) will change the output into a low duty cycle PWM (selective thermal shut-

down with restart) to prevent critical chip temperatures.

SPI Signal Description

CS

pin. Whenever the pin is in a logic low state, data can be transferred from the µC and vice

versa.

CS

High to Low transition: - diagnostic status information is transferred from the power

outputs into the shift register.

- serial input data can be clocked in from then on

- SO changes from high impedance state to logic high or low

state corresponding to the SO bits

CS

Low to High transition: - transfer of SI bits from shift register into output buffers

- reset of diagnosis register

To avoid any false clocking the serial clock input pin SCLK should be logic low state during

pins are ignored and SO is forced into a high impedance state.

SCLK - Serial Clock. The system clock pin clocks the internal shift register of the TLE

6230 GP. The serial input (SI) accepts data into the input shift register on the falling edge of

SCLK while the serial output (SO) shifts diagnostic information out of the shift register on the

rising edge of serial clock. It is essential that the SCLK pin is in a logic low state whenever

chip select cycle. The received data will only be accepted, if exactly 16 clock pulses were

SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit first. SI infor-

mation is read in on the falling edge of SCLK. Input data is latched in the shift register and

then transferred to the control buffer of the output stages.

The input data consists of two bytes - a "control byte” followed by a "data byte". The control

byte contains the information as to whether the data byte will be accepted or ignored (see di-

agnostics section). The data byte contains the input information for the eight channels. A logic

8)

The integrated protection functions prevent an IC destruction under fault conditions and may not be used in normal operation or perma-

nently