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XIO2001IPNP Fiches technique(PDF) 125 Page - Texas Instruments

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No de pièce XIO2001IPNP
Description  PCI Express to PCI Bus Translation Bridge
PDF  141 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

XIO2001IPNP Fiches technique(HTML) 125 Page - Texas Instruments

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XIO2001
www.ti.com
SCPS212I – MAY 2009 – REVISED JANUARY 2016
Product Folder Links: XIO2001
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Copyright © 2009–2016, Texas Instruments Incorporated
Layout (continued)
All 32 bit PCI slots must be placed so the slot can be put on the board as either a 3 V or a 5 V slot. All pins used
as keying pins (A12, A13, A50, A51, B12,B13, B50, B51) should be put on the board and connected to the GND
plane. Mounting holes must be placed on either side of the socket.
(CTXn + TXn) and (CTXp + TXp) are a 100 W differential impedance pair (50 W single ended) and must be
length matched to within 5 mils. i.e. CTXp must be within 5 mils of CTXn, TXp must be within 5 mils of TXn, and
(CTXp + TXp) must be within 5 mils of (CTXn + TXn). The coupling capacitors must be placed as close to the
PCI Express Edge connector as possible.
RXp and RXn are a 100 W differential impedance pair (50 W single ended) and must be length matched to within
5 mils.
9.3.2 Layout Example
Figure 32. BGA Via Routing Layout



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