STM32F401CC datasheet(62/134 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F401xB STM32F401xC

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DocID024738 Rev 5

6.3.4

Operating conditions at power-up / power-down (regulator OFF)

Subject to general operating conditions for TA.

Note:

This feature is only available for UFBGA100 package.

6.3.5

Embedded reset and power control block characteristics

The parameters given in Table 19 are derived from tests performed under ambient

temperature and VDD supply voltage @ 3.3V.

Table 18. Operating conditions at power-up / power-down (regulator OFF)(1)

1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when VDD reach below

1.08 V.

Symbol

Parameter

Conditions

Min

Max

Unit

tVDD

VDD rise time rate

Power-up

∞

µs/V

VDD fall time rate

Power-down

∞

tVCAP

VCAP_1 and VCAP_2 rise time rate Power-up

∞

VCAP_1 and VCAP_2 fall time rate

Power-down

∞

Table 19. Embedded reset and power control block characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VPVD

Programmable voltage

detector level selection

PLS[2:0]=000 (rising edge)

2.09

2.14

2.19

PLS[2:0]=000 (falling edge)

1.98

2.04

2.08

PLS[2:0]=001 (rising edge)

2.23

2.30

2.37

PLS[2:0]=001 (falling edge)

2.13

2.19

2.25

PLS[2:0]=010 (rising edge)

2.39

2.45

2.51

PLS[2:0]=010 (falling edge)

2.29

2.35

2.39

PLS[2:0]=011 (rising edge)

2.54

2.60

2.65

PLS[2:0]=011 (falling edge)

2.44

2.51

2.56

PLS[2:0]=100 (rising edge)

2.70

2.76

2.82

PLS[2:0]=100 (falling edge)

2.59

2.66

2.71

PLS[2:0]=101 (rising edge)

2.86

2.93

2.99

PLS[2:0]=101 (falling edge)

2.65

2.84

2.92

PLS[2:0]=110 (rising edge)

2.96

3.03

3.10

PLS[2:0]=110 (falling edge)

2.85

2.93

2.99

PLS[2:0]=111 (rising edge)

3.07

3.14

3.21

PLS[2:0]=111 (falling edge)

2.95

3.03

3.09

VPVDhyst(2) PVD hysteresis

100

VPOR/PDR

Power-on/power-down

reset threshold

Falling edge

1.60(1) 1.68

1.76

Rising edge

1.64

1.72

1.80

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