USB2642 datasheet(15/56 Pages) MICROCHIP

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 2014-2015 Microchip Technology Inc.

DS00001578C-page 15

USB2642

5.4

ROM Boot Sequence

After power-on reset, the internal firmware checks for an external SPI flash device that contains a valid signature of

2DFU

(device firmware upgrade) beginning at address 0xFFFA. If a valid signature is found, then the external ROM is

enabled and code execution begins at address 0x0000 in the external SPI device. Otherwise, code execution continues

from the internal ROM.

The SPI ROM required for the USB2642 is a recommended minimum of 1 Mbit and support 60 MHz. The frequency

used is set using the SPI_SPD_SEL. For 60 MHz operation, this pin must pulled up through a 100 kΩ resistor. SPI_SP-

D_SEL is used to choose the speed of the SPI interface. During RESET_N assertion, this pin will be tri-stated with the

weak pull-down resistor enabled. When RESET_N is negated, the value on the pin will be internally latched, and the pin

will revert to SPI_DO functionality, and the internal pull-down is disabled.

The firmware can determine the speed of operation on the SPI port by checking the SPI_SPEED in the SPI_CTL Register

(0x2400 - RESET = 0x02). Both 1- and 2-bit SPI operation is supported. For optimum throughput, a 2-bit SPI ROM is

recommended. Both mode 0 and mode 3 SPI ROMS are also supported.

FIGURE 5-3:

PORT POWER WITH GANGED CONTROL WITH POLY FUSE

USB

Device

Poly Fuse

5 V

USB

Device

PRTCTL2

PRTCTL3

USB2642

USB2642 Fiches technique(PDF) 15 Page - Microchip Technology