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AP3598A Fiches technique(PDF) 21 Page - Diodes Incorporated |
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AP3598A Fiches technique(HTML) 21 Page - Diodes Incorporated |
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21 / 28 page ![]() AP3598A Document number: DS37261 Rev. 2 - 2 21 of 28 www.diodes.com November 2014 © Diodes Incorporated AP3598A A Product Line of Diodes Incorporated Application Information (Cont.) 3. Place the first zero fZ1 before the output LC filter double pole frequency fLC. LC Z f f 75 . 0 1 Calculate the C2 by the equation: 75 . 0 2 2 1 2 LC f R C 4. Set the pole at the ESR zero frequency fESR: ESR P f f 1 Calculate the C1 by the following equation: 1 2 2 2 2 1 ESR f C R C C 5. Set the second pole fP2 at the half of the switching frequency and also set the second zero fZ2 at the output LC filter double pole fLC. The compensation gain should not exceed the error amplifier open loop gain. Check the compensation gain at fP2 with the capabilities of the error amplifier. LC Z SW P f f f f 2 2 5 . 0 Combine the two equations will get the following component calculations: 1 2 1 3 LC SW f f R R SW f R C 3 1 3 Figure 15. Converter Gain and Frequency |
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