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Z80C3010VSC Fiches technique(PDF) 55 Page - Zilog, Inc. |
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Z80C3010VSC Fiches technique(HTML) 55 Page - Zilog, Inc. |
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55 / 96 page ![]() =&=& &026 6&& 6HULDO &RPPXQLFDWLRQV &RQWUROOHU )XQFWLRQDO 'HVFULSWLRQ 36 )LJXUH 5HDG 5HJLVWHU %LW)XQFWLRQV D7 D6 D5 D4 D3 D2 D1 D0 Read Register 0 Rx Character Available Zero Count Tx Buffer Empty DCD Sync/Hunt CTS Tx Underrun/EOM Break/Abort D7 D6 D5 D4 D3 D2 D1 D0 Read Register 1 All Sent Residue Code 2 Residue Code 1 Residue Code 0 Parity Error Rx Overrun Error CRC/Framing Error End of Frame (SDLC) D7 D6 D5 D4 D3 D2 D1 D0 Read Register 2 V0 V1 V2 V3 V4 V5 V6 V7 Interrupt Vector * * Modified in B Channel D7 D6 D5 D4 D3 D2 D1 D0 Read Register 12 TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7 Lower Byte of Time Constant D7 D6 D5 D4 D3 D2 D1 D0 Read Register 10 0 On Loop 0 0 Loop Sending 0 Two Clocks Missing One Clocks Missing D7 D6 D5 D4 D3 D2 D1 D0 Read Register 3 Channel B Ext/Status IP Channel B Tx IP Channel B Rx IP Channel A Ext/Status IP Channel A Tx IP Channel A Rx IP 0 0 * * Always 0 in B Channel |
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