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ML4826IP-2 Fiches technique(PDF) 12 Page - Micro Linear Corporation

No de pièce ML4826IP-2
Description  PFC and Dual Output PWM Controller Combo
PDF  16 Pages
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Fabricant  MICRO-LINEAR [Micro Linear Corporation]
Site Internet  http://www.microlinear.com
Logo MICRO-LINEAR - Micro Linear Corporation

ML4826IP-2 Fiches technique(HTML) 12 Page - Micro Linear Corporation

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ML4826
12
current source. The circuit guarantees that the maximum
operating current is available at all times and minimizes
the worst case power dissipation in the IC.
Other methods such as a simple series resistor are
possible, but can very easily lead to excessive ICC current
in the ML4826. Figures 6 and 7 show other possible
methods for feeding VCC.
LEADING/TRAILING MODULATION
Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn on right after the trailing edge of the system clock. The
error amplifier output voltage is then compared with the
modulating ramp. When the modulating ramp reaches the
level of the error amplifier output voltage, the switch will
be turned OFF. When the switch is ON, the inductor
current will ramp up. The effective duty cycle of the
trailing edge modulation is determined during the ON
time of the switch. Figure 4 shows a typical trailing edge
control scheme.
In the case of leading edge modulation, the switch is
turned OFF right at the leading edge of the system clock.
When the modulating ramp reaches the level of the error
amplifier output voltage, the switch will be turned ON.
The effective duty-cycle of the leading edge modulation is
determined during the OFF time of the switch. Figure 5
shows a leading edge control scheme.
One of the advantages of this control technique is that it
requires only one system clock. Switch 1 (SW1) turns off
and switch 2 (SW2) turns on at the same instant to
minimize the momentary “no-load” period, thus lowering
ripple voltage generated by the switching action. With
such synchronized switching, the ripple voltage of the first
stage is reduced. Calculation and evaluation have shown
that the 120Hz component of the PFC’s output ripple
voltage can be reduced by as much as 30% using this
method.
FUNCTIONAL DESCRIPTION (Continued)
ML4826
VCC
RTN
RECTIFIED
VAC
20V
1
µF
1500
µF
39k
Ω
18
Ω
GATE
DRIVE
22k
Ω
T1
Q2
MJE200
Q1
2N2222
ML4826
VCC
RTN
VBIAS
1
µF
ML4826
VCC
RTN
VBIAS
Figure 5. VCC Bias Circuitry
Figure 6.
Figure 7.



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