W97AH6KB datasheet(39/127 Pages) WINBOND

39 / 127 page

W97AH6KB / W97AH2KB

Publication Release Date: May 15, 2014

Revision: A01-001

- 39 -

7.4.8

Write Data Mask

One write data mask (DM) pin for each data byte (DQ) will be supported on LPDDR2 devices, consistent with the

implementation on LPDDR SDRAMs. Each data mask (DM) may mask its respective data byte (DQ) for any given

cycle of the burst. Data mask has identical timings on write operations as the data bits, though used as input only, is

internally loaded identically to data bits to insure matched system timing.

See 7.4.14.2

“Precharge & Auto Precharge Clarification” table for Write to Precharge timings.

7.4.8.1

Write Data Mask Timing

Data Mask Timing

tDH

tDS

tDH

VIH(ac)

VIL(ac)

VIH(dc)

VIL(dc)

VIH(ac)

VIL(ac)

VIH(dc)

VIL(dc)

[Cmd]

WL = 2

Wirte

tDQSSmin

tDQSSmax

tWR

tWTR

Case 2: max tDQSS

Case 1: min tDQSS

Data Mask Function,WL= 2, BL=4 shown,second DQ masked

DQS_c

DQS_t

CK_c

CK_t

DQS_c

DQS_t

DQS_c

DQS_t

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