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S1011 Fiches technique(PDF) 33 Page - Seiko Instruments Inc |
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S1011 Fiches technique(HTML) 33 Page - Seiko Instruments Inc |
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33 / 43 page ![]() HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR Rev.1.2_00 S-1011 Series Seiko Instruments Inc. 33 10. Dynamic response vs. Output pin capacitance (COUT) (CP pin, CN pin; open) 10. 1 VDD detection product S-1011A50 Ta = −40°C 0.00001 0.001 Output pin capacitance [ F] 10 1 0.1 0.01 0.1 0.0001 0.01 0.001 tPHL tPLH S-1011A50 Ta = +25°C 0.00001 0.001 Output pin capacitance [ F] 10 1 0.1 0.01 0.1 0.0001 0.01 0.001 tPHL tPLH S-1011A50 Ta = +85°C 0.00001 0.001 Output pin capacitance [ F] 10 1 0.1 0.01 0.1 0.0001 0.01 0.001 tPHL tPLH tPLH 1 s1 s VIH*1 Input voltage Output voltage VIL*2 VDD1 VDD1 50% VDD1 50% tPHL VDD VSS OUT CP CN VDD R 100 k Ω V + V + VDD1 *1. VIH = 36.0 V *2. VIL = 3.0 V Figure 43 Test Condition of Response Time Figure 44 Test Circuit of Response Time Caution The above connection diagram and constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. |
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