ICS83940DYI REVISION C MARCH 20, 2013

2

©2013 Integrated Device Technology, Inc.

ICS83940DI Data Sheet

LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER

Pin Descriptions and Characteristics

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number

Name

Type

Description

1, 2, 12, 17, 25

GND

Power

Power supply ground.

3

LVCMOS_CLK

Input

Pulldown

Single-ended clock input. LVCMOS/LVTTL interface levels.

4

CLK_SEL

Input

Pulldown

Clock select input. When HIGH, selects LVCMOS_CLK input.

When LOW, selects PCLK, nPCLK inputs.

LVCMOS / LVTTL interface levels.

5

PCLK

Input

Pulldown

Non-inverting differential LVPECL clock input.

6

nPCLK

Input

Pullup/

Pulldown

7, 21

Power

Power supply pin.

8, 16, 29

Power

Output supply pins.

9, 10, 11,

13, 14, 15,

18, 19, 20,

22, 23, 24,

26, 27, 28,

30, 31, 32

Q17, Q16, Q15,

Q14, Q13, Q12,

Q11, Q10, Q9,

Q8, Q7, Q6,

Q5, Q4, Q3,

Q2, Q1, Q0

Output

Single-ended clock outputs. LVCMOS/LVTTL interface levels.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input Capacitance

4

pF

Input Pullup Resistor

51

k



Input Pulldown Resistor

51

k



Power Dissipation Capacitance

(per output)

6pF

Output Impedance

18

28

