Low-Voltage, CMOS Analog Multiplexers/Switches

with Enable Inputs and Address Latching

______________________________________________________________________________________

11

Figure 2. Enable Switching Time

_________________________________Test Circuits/Timing Diagrams (continued)

50%

0V

0V

V-

COM

V-

300

Ω

GND

ADDC

ADDB

ADDA

EN1

V+

50

Ω

90%

90%

35pF

V+

V+

V+

MAX4530

NO1–NO7

NO0

+3V

EN2

V-

COM_

V-

300

Ω

GND

ADDA

ADDB

EN1

50

Ω

35pF

V+

V+

V+

MAX4531

NO1_, N02_, NO3_

NO0_

+3V

EN2

50%

0V

0V

V+

90%

90%

V-

COM_

V-

300

Ω

GND

ADD_

EN1

50

Ω

35pF

V+

V+

V+

MAX4532

NC_

NO_

+3V

EN2

50%

0V

0V

V+

90%

90%

V- = 0V FOR SINGLE-SUPPLY OPERATION.

REPEAT TEST FOR EACH SECTION.

REPEAT TEST FOR EN2, WITH PULSE INVERTED

AND EN1 CONNECTED TO GND.

LE

LE

LE