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LTC8143FSW Fiches technique(PDF) 6 Page - Linear Technology

No de pièce LTC8143FSW
Description  Improved Industry Standard Serial 12-Bit Multiplying DACs
PDF  8 Pages
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Fabricant  LINER [Linear Technology]
Site Internet  http://www.linear.com
Logo LINER - Linear Technology

LTC8143FSW Fiches technique(HTML) 6 Page - Linear Technology

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LTC7543/LTC8143
TRUTH TABLES
Table 1. LTC7543/LTC8143 Input Register
CONTROL INPUTS
Input Register Operation
STB1 STB2 STB3 STB4
(LTC8143: SRO Operation)
0
1
0
Serial Data Bit on SRI Loaded into Input
0
1
0
Register, MSB First
0
0
0
(LTC8143: Data Bit or SRI Appears on
0
0
1
SRO Pin After 12 Clocked Bits)
1
X
X
X
No Input Register Operation
X
1
X
X
(LTC8143: No SRO Operation)
X
X0X
XXX
1
Table 2. LTC7543/LTC8143 DAC Register
CONTROL INPUTS
CLR
LD1
LD2
DAC Register Operation
0
X
X
Reset DAC Register to All 0s (Asynchronous
Operation; No Effect on Input Register)
1
1
X
No DAC Register Operation
1X
1
1
0
0
Load DAC Register with the Contents of Input
Register
TYPICAL APPLICATIONS
VDD VREF
LTC7543
LTC8143
RFB
AGND
DGND
3
12
10
4
7
5
6
9
8
11
2
14
13
5V
VREF
–10V TO 10V
TO NEXT DAC
FOR DAISY-CHAINING
(LTC8143)
15
16
1
OUT 1
33pF
0.1
µF
VOUT
0V TO –VREF
7543/8143 TA03
OUT 2
LT1097
CLR
STB3
STB1
SRI
LD1
SRO (LTC8143)
LD2
STB2
STB4
µP
Unipolar Operation (2-Quadrant Multiplication)
DIGITAL INPUT
BINARY NUMBER IN
ANALOG OUTPUT
DAC REGISTER
VOUT
MSB
LSB
1111
1111
1111
– VREF (4095/4096)
1000
0000
0000
– VREF (2048/4096) = – VREF/2
0000
0000
0001
– VREF (1/4096)
0000
0000
0000
0V
Unipolar Binary Code Table



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