LTC1405IGN datasheet(4/16 Pages) LINER

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LTC1405

DIGITAL I PUTS AND OUTPUTSThe q denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply

operation. (Note 5)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

POWER REQUIRE E TS The q denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation.

(Note 5)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

VDD

Positive Supply Voltage

(Note 10)

4.75

5.25

VSS

Negative Supply Voltage

Dual Supply Mode

– 5.25

– 4.75

Single Supply Mode

IDD

Positive Supply Current

ISS

Negative Supply Current

0.8

1.2

Power Dissipation

115

145

TI I G CHARACTERISTICS The q denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation.

(Note 5)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

fSAMPLE

Sampling Frequency

0.02

MHz

tCONV

Conversion Time

150

180

tACQ

Acquisition Time

CLK High Time

(Note 9)

100

CLK Low Time

(Note 9)

100

tAD

Aperture Delay of Sample-and-Hold

– 250

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: All voltage values are with respect to ground with GND and OGND

wired together (unless otherwise noted).

Note 3: When these pin voltages are taken below VSS or above VDD, they

will be clamped by internal diodes. This product can handle input currents

greater than 100mA below VSS or above VDD without latchup.

Note 4: When these pin voltages are taken below VSS they will be clamped

by internal diodes. This product can handle input currents greater than

100mA below VSS without latchup. GAIN is not clamped to VDD. When CLK

is taken above VDD, it will be clamped by an internal diode. The CLK pin

can handle input currents of greater than 100mA above VDD without

latchup.

Note 5: VDD = 5V, VSS = – 5V or 0V, fSAMPLE = 5MHz, tr = tf = 5ns unless

otherwise specified.

IIN

Digital Input Current

VIN = 0V to VDD

±10

µA

CIN

Digital Input Capacitance

1.8

VOH

High Level Output Voltage

0VDD = 4.75V, IO = –10µA

4.74

0VDD = 4.75V, IO = –200µA

4.0

4.71

0VDD = 2.7V, IO = –10µA

2.6

0VDD = 2.7V, IO = –200µA

2.3

VOL

Low Level Output Voltage

0VDD = 4.75V, IO = 160µA

0.05

0VDD = 4.75V, IO = 1.6mA

0.10

0.4

0VDD = 2.7V, IO = 160µA

0.05

0VDD = 2.7V, IO = 1.6mA

0.10

0.4

ISOURCE

Output Source Current

VOUT = 0V

ISINK

Output Sink Current

VOUT = VDD

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