PM0056 datasheet(101/156 Pages) STMICROELECTRONICS

101 / 156 page

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PM0056

The Cortex-M3 instruction set

where:

•

‘cond’ is an optional condition code, see Conditional execution on page 57.

•

‘Rd’ is the destination register.

•

‘spec_reg’ can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP,

PSP, PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.

Operation

Use MRS in combination with MSR as part of a read-modify-write sequence for updating a

PSR, for example to clear the Q flag.

In process swap code, the programmers model state of the process being swapped out

must be saved, including relevant PSR contents. Similarly, the state of the process being

swapped in must also be restored. These operations use MRS in the state-saving

instruction sequence and MSR in the state-restoring instruction sequence.

BASEPRI_MAX is an alias of BASEPRI when used with the MRS instruction.

See MSR on page 101.

Restrictions

Rd must not be SP and must not be PC.

Condition flags

This instruction does not change the flags.

Examples

MRS

R0, PRIMASK ; Read PRIMASK value and write it to R0

3.9.7

MSR

Move the contents of a general-purpose register into the specified special register.

Syntax

MSR{cond} spec_reg, Rn

where:

•

‘cond’ is an optional condition code, see Conditional execution on page 57.

•

‘Rn’ is the source register.

•

‘spec_reg’ can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP,

PSP, PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.

Operation

The register access operation in MSR depends on the privilege level. Unprivileged software

can only access the APSR, see Table 4: APSR bit definitions on page 17. Privileged

software can access all special registers.

In unprivileged software writes to unallocated or execution state bits in the PSR are ignored.

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