UPD6345GS datasheet(2/16 Pages) NEC

2 / 16 page

µPD6345

PIN CONFIGURATION (Top View)

PIN IDENTIFICATION

Pin No.

Symbol

Pin name

Input/Output

Function

GND

Ground

—

Connection to Ground (GND) of system.

Output Enable

Input

When this pin is low or open, all outputs are OFF, and data is output

during high.

LAT

Latch Enable

Input

When this pin is low or open, data is latched and data is through to

output during high.

Serial data Output

Output

Serial data is output on positive-going transition of the clock.

In case of connection to cascade additional device (

µPD6345), this

pin will be connected to SIN terminal of additional device.

5 to 12

O8 to O1

Driver Output

Output

High Voltage and Current Driver Outputs.

SIN

Serial data Input

Input

Data is loaded to shift register on positive-going transition.

SCK

Clock

Input

Data of SIN is loaded to shift register on positive-going transition of

SCK. Also, serial data is output from SO on positive-going transition

of SCK.

RES

Reset

Input

When this pin is low or open, data of shift register is all cleared, and

this device operate normally during high.

VDD

Power Supply

—

Normally supply 5 V.

VSS

LAT

VDD

RES

SCK

SIN

UPD6345GS Fiches technique(PDF) 2 Page - NEC

UPD6345GS Fiches technique(HTML) 2 Page - NEC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Fiches technique Télécharger

Lien URL