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ST9 EXTERNAL MEMORY INTERFACE CONFIGURATION

4 EXTERNAL MEMORY INTERFACE FOR OLD ST9 DEVICES

– Some older ST9 devices output the MSB of the address on port2 and LSB on either port0/

port 6 based on the NMB bit:

– I/O Port 2 (6 pins): outputs the MMU bits of the address (A[16..21]).

– I/O Port 6 (8 pins): if the non-multiplexed bus option is chosen, this port outputs the LSB of

the address (A[0..7]). In this case, Port 0 only outputs the 8 bits of data (D[0..7]).

4.1 NON-MULTIPLEXED BUS (NMB BIT 3): LARGE MEMORY MODEL OPTION

When this bit is zero, Port 0 outputs the multiplexed data and the LSB of the address. When

this bit is 1, it is port 6 which outputs the address LSB (Port 0 is released in high impedance

during this time), and Port 0 only outputs data.

Figure 6 shows an example for a Large Memory Model, where the non-multiplexed bus (NMB

bit of the EMR1 register) and the second Data Strobe (DS2EN bit of the EMR1 register) op-

tions have been chosen. This allows some external hardware devices like the latch to be

saved.

Figure 6. Hardware Implementation: Large Memory Model Example

ROM

512 Kbytes

RAM

64 Kbytes

G

E

E

Q0-Q7

A0-A15

A7-A0

A15-A8

A20-A16

A21

A0-A18

DQ0-DQ7

G

W

ST9

RWN

DSN

P0

DS2N

P2

P1

P6