RM0352 datasheet(122/138 Pages) STMICROELECTRONICS

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UART (universal asynchronous receive transmit)

RM0352

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DocID024647 Rev 1

12.6.3

Flag register, UARTFR

The UARTFR register is the flag register. After reset TXFF, RXFF, and BUSY are 0, and

TXFE and RXFE are 1.

Table 117 lists the register bit assignments.

2BE

Break error. This bit is set to 1 if a break condition was detected, indicating that the received data

input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and

stop bits).

This bit is cleared to 0 after a write to UARTECR.

In the FIFO mode, this error is associated with the character at the top of the FIFO. When a break

occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the

receive data input goes to a 1 (marking state) and the next valid start bit is received.

1PE

Parity error. When set to 1, it indicates that the parity of the received data character does not match

the parity that the EPS and SPS bits in the line control register, UARTLCR_H

Section 12.6.7 on

page 126 select.

This bit is cleared to 0 by a write to UARTECR.

In the FIFO mode, this error is associated with the character at the top of the FIFO.

0FE

Framing error. When set to 1, it indicates that the received character did not have a valid stop bit

(a valid stop bit is 1).

This bit is cleared to 0 by a write to UARTECR.

In the FIFO mode, this error is associated with the character at the top of the FIFO.

The received data character must be read first from the data register, UARTDR

Section 12.6.1 on page 120 before reading

the error status associated with that data character from the UARTRSR register. This read sequence cannot be reversed,

because the UARTRSR register is updated only when a read occurs from the UARTDR register. However, the status

information can also be obtained by reading the UARTDR register.

Table 116. UARTRSR/UARTECR register(1) (continued)

Bits

Name

Function

Table 117. UARTFR register

Bits

Name

Function

15:9

RESERVED, do not modify, read as zero.

8RI

Ring indicator. This bit is the complement of the UART ring indicator,

nUARTRI, modem status

input. That is, the bit is 1 when

nUARTRI is LOW.

7TXFE

Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the line control

Section 12.6.7 on page 126.

If the FIFO is disabled, this bit is set when the transmit holding register is empty.

If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty.

This bit does not indicate if there is data in the transmit shift register.

6RXFF

Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H

If the FIFO is disabled, this bit is set when the receive holding register is full.

If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full.

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