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AN2960 Fiches technique(PDF) 21 Page - STMicroelectronics |
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AN2960 Fiches technique(HTML) 21 Page - STMicroelectronics |
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21 / 41 page ![]() AN2960 About control registers Doc ID 15557 Rev 1 21/41 Figure 10 shows the block diagram of the digital processing chain and the related control signals. Figure 10. Digital processing chain block diagram 6.3 CTRL_REG3 (22h) Control register #3. HP Filter Interrupt Generator (FF_WU 1) CTRL_REG2(HP FF_WU1) 0 CTRL_REG3(FDS) 0 Regs Array Digital Processing Chain HP_FILTER_RESET 1 1 Interrupt Generator (FF_WU 2) CTRL_REG2(HP FF_WU2) 0 1 Offset Output regs SRC reg 1 SRC reg 2 Adjustment Block IHL PP_OD I2CFG2 I2CFG1 I2CFG0 I1CFG2 I1CFG1 I1CFG0 IHL Interrupt active high, low. Default value 0. (0: active high; 1: active low) PP_OD Push-pull/open drain selection on interrupt pad. Default value 0. (0: push-pull; 1: open drain) I2CFG2, I2CFG0 Interrupt 2 configuration bits. Default value 000. (see table below) I1CFG2, I1CFG0 Interrupt 1 configuration bits. Default value 000. (see table below) |
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