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AN832 Fiches technique(PDF) 1 Page - STMicroelectronics |
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AN832 Fiches technique(HTML) 1 Page - STMicroelectronics |
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1 / 3 page ![]() 1/3 AN832 APPLICATION NOTE November 2003 Devices Description In most of SMPS using power factor correction, the convertion is accomplished with a PFC stage, in boost to- pology, that delivers a preregulated DC voltage to a downstream section. This provides the regulated final DC buses, ensuring also the galvanic insulation from the mains. Both sections use a P.W.M. technique each with their own control. This means that two different switch mode controllers work very close one to the other producing some potential problem (eg. interferences, beating etc.). The L4981A controller is provided with an input/output (I/O) synchronization pin (see datasheet pin16 descrip- tion) which allows the device to be used both as a master or a slave in synchronised configuration. Let us take into consideration how to interface the L4981A with other PWM controllers each requiring different interconnections. The devices that have been considered in the following examples are the L4990 (PWM pri- mary contoller provided with I/O sync.) and the UC3842 PWM controller without any dedicated pin for sync.). When L4990 with L4981A are used, different situations can be considered : The PFC controller L4981A is the master and the L4990 is the slave (see fig. 1). Since the L4990 is provided with a positive edge input sync., the two sync. pins can be simply wired together. The L4990 is the master and the L4981A is the slave (see fig. 2). Figure 1. Sync. example with L4981A used as master. Figure 2. Sync. example with L4981A used as slave L4981A L4990 (fsw1)OSC (fsw2)OSC fsw1 > fsw2 16 1 D95IN293A MASTER SLAVE L4981A L4990 (fsw1)OSC (fsw2)OSC fsw1 > fsw2 1 16 D95IN294A Ref 47pF MASTER SLAVE by C. Adragna L4981A SYNCHRONIZATION |
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