UPD17072 datasheet(13/226 Pages) NEC

13 / 226 page

µPD17072,17073

Pin No.

Symbol

Function

Output format

At power-ON

QFP

TQFP

reset

VDD

Positive power supply.

—

Supply 1.8 to 3.6 V (TA = –20 to +70

°C) to operate

all functions.

Do not apply voltage higher than that of VDD pin to

any pin other than VDD.

XOUT

Pins for connecting crystal resonator for system

CMOS push-pull

—

XIN

clock oscillation.

—

REG1

Output of voltage regulator for oscillation circuit.

—

Connect this pin to GND via 0.1-

µF capacitor.

REGLCD0

• REGLCD1, REGLCD0—

—

CAPLCD0

LCD drive power pins.

CAPLCD1

• CAPLCD1, CAPLCD0

REGLCD1

Connect capacitors for doubler circuit to generate

LCD drive voltage, across these pins.

To configure doubler circuit, connect capacitors

as shown below.

Caution The value of the LCD drive voltage differs

if the values of C1, C2, and C3 are changed

because of the configuration of the doubler

circuit.

REG1

0.1 F

REGLCD1

CAPLCD1

CAPLCD0

REGLCD0

C1 = C2 = 0.1 F

C3 = 0.01 F

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