HS8-RTX2010RH-Q datasheet(21/36 Pages) INTERSIL

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HS-RTX2010RH Interrupt Controller

The HS-RTX2010RH Interrupt Controller manages interrupts

for the HS-RTX2010RH Microcontroller core. Its sources

include two on-chip peripherals and six external interrupt

inputs. The two classes of on-chip peripherals that produce

interrupts are the Stack Controllers and the Timer/Counters.

Interrupt Controller Operation

When one of the interrupt sources requests an interrupt, the

Interrupt Controller checks whether the interrupt is masked

in the Interrupt Mask Register. If it is not, the controller

attempts to interrupt the processor. If processor interrupts

are enabled (bit 4 of the Conﬁguration Register), the

processor will execute an Interrupt Acknowledge cycle,

during which it disables interrupts to ensure proper

completion of the INTA cycle.

In response to the Interrupt Acknowledge cycle, the Interrupt

Controller places an Interrupt Vector on the internal ASIC

Bus, based on the highest priority pending interrupt. The

processor performs a special Subroutine Call to the address

in Memory Page 0 contained in the vector. This special

subroutine call is different in that it saves a status bit on the

Return Stack indicating the call was caused by an interrupt.

Thus, when the Interrupt Handler executes a Subroutine

Return, the processor knows to automatically re-enable

interrupts. Before the Interrupt Handler returns, it must

ensure that the condition that caused the interrupt is cleared.

Otherwise the processor will again be interrupted

immediately upon its return.

Processor interrupts are enabled and disabled by clearing

and setting the Interrupt Disable Flag. When the RTX is

reset, this ﬂag is set (bit 04 of the

= 1), disabling the

interrupts. This bit is a write-only bit that always reads as 0,

allowing interrupts to be enabled in only 2 cycles with a

simple read/write operation in which the processor reads the

bit value, then writes it back to the same location. The actual

status of the Interrupt Disable Flag can be read from bit 14

ACTIVATE

TIMEOUT

INTERRUPT

ACTIVATE

TIMEOUT

INTERRUPT

ACTIVATE

TIMEOUT

INTERRUPT

EXECUTE

COUNT

EXECUTE

COUNT

EXECUTE

COUNT

INTERRUPT

RESET

INTERRUPT

RESET

INTERRUPT

RESET

INTERRUPT

CONTROLLER

PRELOAD

TP2

INTA CYCLE OR

ASIC READ COMMAND

LOAD

TC0

RISING

EDGE

TCLK

RISING

EDGE

TCLK

PRELOAD

TP0

TIMER/COUNTER

LOAD

TC1

TIMER/COUNTER

LOAD

TC2

PRELOAD

TP1

TOP

FIGURE 23. HS-RTX2010RH TIMER/COUNTER OPERATION

TABLE 3. TIMER/COUNTER

BIT VALUES

TIMER CLOCK SOURCE

BIT 09

BIT 08

TCLK

EI3

TCLK

EI4

EI3

EI5

EI4

EI3

IBC

TC2

TC1

TC0

HS-RTX2010RH

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