UPC1935 datasheet(13/28 Pages) NEC

13 / 28 page

Data Sheet G13418EJ3V0DS00

µµµµ PC1935

2.6

Timer Latch-Method Short Circuit Protection Circuit

When the outputs of the converters for each channel drop, the FB outputs of the error amplifiers of those outputs go

high (FB3 output goes low). If the FB output exceeds the timer latch input detection voltage (VTH = 1.9 V) (FB3 output goes

lower than the timer latch input detection voltage (VTH = 0.63 V)), then the output of the SCP comparator goes low, and Q1

goes off.

When Q1 turns OFF, the constant-current supply charges CDLY via the DLY pin. The DLY pin is internally connected to a

flip-flop. When the DLY pin voltage reaches the UV detection voltage (VUV = 0.8 V (TYP.)), the output Q of the flip-flop goes

low, and the output stage of each channel is latched to OFF (refer to Figure 2-1 Block Diagram).

The logic of channels 1 and 2 is reverse to that of channel 3. Consequently, an inverter circuit is inserted between the

FB output of channels 1 and 2, and SCP comparator input.

Make the power supply voltage briefly less than the reset voltage (VCCR, 1.0 V TYP.) to reset the latch circuit when the

short-circuit protection circuit has operated.

2.7

Output Circuit

The output circuit has an N-channel open-drain output providing an output withstand voltage of 30 V (absolute maximum

rating), and an output current of 21 mA (absolute maximum rating).

UPC1935 Fiches technique(PDF) 13 Page - NEC