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CDP1823CDX Fiches technique(PDF) 5 Page - Intersil Corporation

No de pièce CDP1823CDX
Description  128-Word x 8-Bit LSI Static RAM
PDF  7 Pages
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Fabricant  INTERSIL [Intersil Corporation]
Site Internet  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CDP1823CDX Fiches technique(HTML) 5 Page - Intersil Corporation

  CDP1823CDX Datasheet HTML 1Page - Intersil Corporation CDP1823CDX Datasheet HTML 2Page - Intersil Corporation CDP1823CDX Datasheet HTML 3Page - Intersil Corporation CDP1823CDX Datasheet HTML 4Page - Intersil Corporation CDP1823CDX Datasheet HTML 5Page - Intersil Corporation CDP1823CDX Datasheet HTML 6Page - Intersil Corporation CDP1823CDX Datasheet HTML 7Page - Intersil Corporation  
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Dynamic Electrical Specifications At TA = -40 to +85oC, VDD ±5%, tR, tF = 20ns, CL = 100pF
PARAMETER
SYMBOL
VDD
(V)
LIMITS
CDP1823
CDP1823C
UNITS
(NOTE 2)
MIN
(NOTE 1)
TYP
MAX
(NOTE 2)
MIN
(NOTE 1)
TYP
MAX
Write Cycle (See Figure 2)
Write Recovery
tWR
5
75-
-75-
-
ns
10
50
-----
ns
Write Cycle
tWC
5
400
-
-
400
-
-
ns
10
225
-----
ns
Write Pulse Width
tWRW
5
200
-
-
200
-
-
ns
10
100
-----
ns
Address Setup Time
tAS
5
125
-
-
125
-
-
ns
10
75
-----
ns
Data Setup Time
tDS
5
100
-
-
100
-
-
ns
10
75
-----
ns
Data Hold Time From MWR
tDH
5
75-
-75-
-
ns
10
50
-----
ns
NOTES:
1. Typical values are at TA = 25
oC and nominal voltage.
2. Time required by a limit device to allow for the indicated function.
ADDRESS
tWC
tAS
tWR
CS1, CS4
CS2, CS3, CS5
tWRW
tDS
tDH
MWR
BUS 0-7
VALID DATA
NOTE:
1. MRD must be high during write operation.
FIGURE 2. WRITE CYCLE TIMING DIAGRAM
CDP1823, CDP1823C



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