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DD28F032SA Fiches technique(PDF) 21 Page - Intel Corporation

No de pièce DD28F032SA
Description  32-MBIT (2 MBIT X 16, 4 MBIT X 8) FlashFile MEMORY
PDF  49 Pages
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Fabricant  INTEL [Intel Corporation]
Site Internet  http://www.intel.com
Logo INTEL - Intel Corporation

DD28F032SA Fiches technique(HTML) 21 Page - Intel Corporation

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DD28F032SA
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6.3 Timing Nomenclature
All 3.3V system timings are measured from where signals cross 1.5V.
For 5.0V systems use the standard JEDEC cross point definitions.
Each timing parameter consists of 5 characters. Some common examples are defined below:
tCE
tELQV time(t) from CEX# (E) going low (L) to the outputs (Q) becoming valid (V)
tOE
tGLQV time(t) from OE # (G) going low (L) to the outputs (Q) becoming valid (V)
tACC
tAVQV time(t) from address (A) valid (V) to the outputs (Q) becoming valid (V)
tAS
tAVWH time(t) from address (A) valid (V) to WE# (W) going high (H)
tDH
tWHDX time(t) from WE# (W) going high (H) to when the data (D) can become undefined (X)
Pin Characters
Pin States
A
Address Inputs
H
High
D
Data Inputs
L
Low
Q
Data Outputs
V
Valid
ECEX# (Chip Enable)
X
Driven, but not necessarily valid
F
BYTE# (Byte Enable)
Z
High Impedance
G
OE# (Output Enable)
W
WE# (Write Enable)
P
RP# (Deep Power-Down Pin)
R
RY/BY# (Ready Busy)
V
Any Voltage Level
Y
3/5# Pin
5V
VCC at 4.5V Minimum
3V
VCC at 3.0V Minimum



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