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IMP1233DZ-5/T Fiches technique(PDF) 4 Page - IMP, Inc |
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IMP1233DZ-5/T Fiches technique(HTML) 4 Page - IMP, Inc |
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4 / 6 page ![]() IMP1 IMP1 233D 233D 4 408-432-9100/www.impweb.com 2000 © IMP, Inc. ! Operation – Power Monitor The IMP1233D detects out-of-tolerance power supply conditions. It resets a processor during power-up and issues a reset to the sys- tem processor when the monitored power supply voltage is below the reset threshold (power-down). When an out-of-tolerance VCC voltage is detected, the RESET signal is asserted. On power-up, RESET is kept active (LOW) for approximately 350ms after the power supply voltage has reached the selected tolerance. This allows the power supply and microprocessor to stabilize before RESET is released. Figure 1. Timing Diagram: Power-Up Figure 2. Timing Diagram: Power-Down VCCTP (MAX) VCCTP VCCTP (MIN) VCC RESET tR tRPU VOH 1233D_06.eps VCCTP (MAX) VCCTP VCCTP (MIN) VCC RESET tF VOL tRPD 1233D_07.eps Application Information |
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