7

ICS9177

Table 8: AC Specification type Out D.ttl Pins

(12.5 MHz)

Test Load Conditions: 500W, 15 pF.

Note 1: Delay is the intrinsic delay between the TTL drivers switching and the PECL driver switching. This is measured from

the OutA.pecl signal at the signal swing mid-point to max output of the OutD.ttl signal’s rising edge

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Output High Voltage

Voh

2.4

5

3.2

volts

Output Low Voltage

Vol

0

0.8

0.3

volts

Output High Current

Ioh

16

mA

Output Low Current

Iol

24

mA

Rise Time 10-90%

tr

1

3

2

ns

Fall Time 10-90%

tf

1

3

2

ns

Pin skew to other OutD.ttl

signals

tsk

500

250

ps

Duty cycle at 1.5V

dcyc

45

55

%

tdly

.5

ns

Skew associated with above

tdlyskw

±1.3

ns