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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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ICS1887M Fiches technique(PDF) 1 Page - Integrated Circuit Systems |
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ICS1887M Fiches technique(HTML) 1 Page - Integrated Circuit Systems |
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1 / 14 page  Integrated Circuit Systems, Inc. General Description Features ICS1887 Block Diagram PHYceiver is a trademark of Integrated Circuit Systems, Inc. FDDI / Fast Ethernet PHYceiverTM ICS1887RevF112596 • Single IC solution to existing designs requiring multiple devices • Data and clock recovery for 125 MBaud FDDI or Fast Ethernet applications • Clock multiplication from either a crystal, differential or single-ended timing source • Continuous clock in the absence of data • No external PLL components • Lock/Loss status indicator output • Loopback mode for system diagnostics • Selectable loop timing mode • PECL driver with settable sink current • Parallel digital transmit and receive data interface • NRZ to/from NRZI data conversion • Consult ICS for optional configurations and data rates The ICS1887 is designed to provide high performance clock recovery and generation for 125 MHz serial data streams. The ICS1887 is ideally suited for LAN transceiver applications in either FDDI or Fast Ethernet environments. The ICS1887 converts NRZ to/from NRZI data in addition to providing a 5-bit parallel digital data transmit and receive interface. Clock and data recovery is performed on an input serial data stream or the buffered transmit data depending upon the state of the loopback input. A continuous clock source will continue to be present even in the absence of input data. All internal timing is derived from either a low cost crystal, differential or single-ended source. The ICS1887 utilizes advanced CMOS phase-locked loop technology which combines high performance and low power at a greatly reduced cost. Pin Configuration 28-Pin SOIC |
Numéro de pièce similaire - ICS1887M |
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Description similaire - ICS1887M |
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