WM8580AGEFTV datasheet(80/106 Pages) WOLFSON

Moteur de recherche de fiches techniques de composants électroniques

WM8580AGEFTV Fiches technique(PDF) 80 Page - Wolfson Microelectronics plc

No de pièce	WM8580AGEFTV

Description	Multichannel CODEC with S/PDIF Transceiver

PDF	106 Pages

Scroll/Zoom	100%

Fabricant	WOLFSON [Wolfson Microelectronics plc]

Site Internet	http://www.wolfsonmicro.com

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80 / 106 page

WM8580A

Production Data

PD, Rev 4.9, November 2013

SLAVE MODE

If the S/PDIF Rx interface is enabled, then an internal MCLK is generated at 256fs. This internal clock

will act as a source clock for ADC, DACs and PAIF. The user is required to supply input clocks to the

PAIFTX_BCLK and the PAIF_LRCLK.

If the PAIF or DACs source the S/PDIF Rx interface then the PAIFTX_BCLK and the PAIF_LRCLK

input clocks must be synchronous to clock driving the S/PDIF interface. If these clocks cannot be

guaranteed synchronous then this mode of operation is not recommended.

If the PAIF sources the ADC data, then the user must supply input clocks to ADCCLK, PAIFTX_BCLK

and the PAIF_LRCLK pins.

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