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ADC10D040CIVS/NOPB Fiches technique(PDF) 2 Page - Texas Instruments |
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ADC10D040CIVS/NOPB Fiches technique(HTML) 2 Page - Texas Instruments |
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2 / 32 page ![]() ADC10D040 SNAS149G – OCT 2001 – REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Connection Diagram Figure 1. TOP VIEW Block Diagram 2 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: ADC10D040 |
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